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The LXT304A is a fully integrated low-power transceiver for both North American 1.544 Mbps (T1), and International 2.048 Mbps (E1) applications. It features a constant low output impedance transmitter allowing for high transmitter return loss in T1/E1 applications. Transmit pulse shapes (DSX-1 or E1) are selectable for various line lengths and cable types. The LXT304A provides receive jitter attenuation starting at 3 Hz, and is microprocessor controllable through a serial interface. It offers a variety of diagnostic features including transmit and receive monitoring. The device incorporates an onchip crystal oscillator, and also accepts digital clock inputs. It uses an advanced double-poly, double-metal CMOS process and requires only a single 5-volt power supply.
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The transceiver incorporates a Driver Performance Monitor (DPM) in parallel with TTIP and TRING at the output transformer. The DPM output goes High upon detection of 63 consecutive zeros. It is reset when a one is detected on the transmit line, or when a reset command is received.
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The LXT304A transmits data as a 50% AMI line code as shown in Figure 2. The output driver maintains a constant low output impedance regardless of whether it is driving marks or spaces.
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Figure 5 is a 2.048 Mbps E1 TWP application using 15 Rt resistors in line with the transmit transformer to provide high return loss and surge protection. When high return loss is not a critical factor, a 1:1 or 1:1.26 transformer without in-line resistors provides maximum power savings. The LXT304A is shown in Hardware Mode with a typical E1/
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Existing D4 Channel Bank architectures frequently employ: (1) a plug-in card for T1 pulse generation (6.0 V peak); and (2) a separate card for pulse shaping and Line Build-Out (LBO). The LXT304A integrates the functions of both cards on a single chip producing a DSX-1 compatible, 3.0 V peak output pulse with a standard transformer. In new designs, the LXT304A can replace two cards with one. However, the LXT304A is also compatible with ex7DEOH ca 7ii(i ,QSXWi2XWSXW &RQILJXUDWLRQV %LW 5DWH o0ESVo iieee o7io &U\VWDO ;7$/ &DEOH oo 5Ue oo eii (&eieii
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ii Power dissipation while driving 75 load over operating temperature range. Includes device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions. 3. Output drivers will output CMOS logic levels into CMOS loads. 4. Except MTIP and MRING ILL = 50 A.
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3. Circuit attenuates jitter at 20 dB/decade above the corner frequency. 4. In accordance with ITU G.703/ETS 300166 return loss specifications when wired per Figure 7 (E1). 5. Guaranteed by design.
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